1. Field of the Invention
The present invention relates in general to memory integrated circuits, particularly but not limitatively to non-volatile memories; more specifically, the invention concerns the implementation of redundancy in memory integrated circuits.
2. Description of the Related Art
An important aspect in the design of Integrated Circuits (ICs) is a careful implementation of redundancy. Generally speaking, implementing redundancy in ICs means duplicating those circuit blocks that are considered more critical for the IC functionality; the duplicated (in jargon, redundant) circuit blocks can thus be exploited for functionally replacing the corresponding main circuit blocks in the event of failures thereof.
Implementing redundancy is of paramount importance in memory ICs, and particularly in high-capacity memories having very large and extremely dense arrays of memory cells.
Especially when a new manufacturing technology is being developed, it is in fact highly probable that manufacturing defects impair the functionality of some of the memory cells in the array. If no precautions were taken in the design phase, the presence of these defects would have a substantial impact on the overall yield of the manufacturing process.
For these reasons, redundancy is widely used in memory ICs.
Redundancy can be implemented in memory ICs in several ways. For example, redundant rows or columns of memory cells can be provided in the memory cell array, for functionally replacing defective rows or columns, e.g., rows or columns containing defective memory cells.
In particular, in Flash memory ICs having memory cell arrays made up of two or more individually alterable memory blocks or sectors (i.e., elemental portions of the memory cell array that can be individually erased in bulk without however altering the content of other portions of the memory array), redundancy is commonly implemented by providing one or more memory sector duplicates, referred to as redundant memory sectors. In this way, a defective memory sector can be functionally replaced by one of the available redundant memory sectors.
A redundancy control circuitry is conventionally provided, capable of storing address codes identifying defective memory sectors which have been functionally replaced by redundant memory sectors; each time a new address code is received by the memory, the redundancy control circuitry compares the received address code to the stored address code, so as to establish whether the memory location identified by the received address code belongs to one of the defective memory sectors. If the addressed memory location does not belong to a defective memory sector, the memory location is normally accessed; on the contrary, if the addressed memory location belongs to a defective memory sector, the normal address decoding and selection circuits that allow selecting the addressed memory location within the memory sector are disabled, and a redundant memory location is instead selected within the redundant memory sector that functionally replaces the defective sector.
In this way, the defective memory sector is kept isolated from any operation of read or alteration of the memory content.
However, the Applicant has observed that this conventional way of implementing sector redundancy in a Flash memory has some drawbacks, which will be discussed hereinbelow.
First of all, when a memory sector is identified as defective, the conventional implementation of redundancy does not really allow completely isolating the defective sector from the normal operation of the memory. For example, the local row address decoder and word line selection circuitry (shortly, the row decoder) associated with the defective memory sector is not actually isolated from the remaining of the IC, being instead still kept powered by the prescribed voltages necessary for reading the memory locations or altering the content thereof, notwithstanding the fact that the associated memory sector is defective and has been functionally replaced by a redundant memory sector. In fact, it is not feasible to delay the act of powering the row decoder so as to condition this act to the outcome of the comparison, performed by the redundancy control circuitry, of the current address code received by the memory to the stored defective address codes: the relatively heavy capacitive loads involved would in fact slow down the reaching of the prescribed voltages, and this would have a negative impact on the access time to the memory. Possible defects within the row decoder may thus cause current leakages that may cause the overall current consumption of the memory IC to exceed specified ratings; even worse, the leakages could be so high that the voltage generators (charge pumps) internal to the memory IC and that generate the voltages used for powering the row decoders are not capable of sustaining them: the output voltages of these generators may thus fall to levels that are too low for ensuring satisfactory performances of the memory.
Another drawback inherent to the conventional implementation of the sector redundancy in Flash memories is the lengthening of the memory access time; the address decoding circuitry of the memory is in fact inevitably affected by the delay inherent to the comparison that needs to be each time performed by redundancy control circuitry between the current address code and the stored address codes of the defective memory sectors.
Normally, when a new address code is received, the address decoding circuitry starts decoding the received address and selecting the corresponding memory location in the addressed memory sector, irrespective of the fact that the memory sector is defective. When the redundancy control circuitry has established that the addressed memory location belongs to a defective memory sector, a corresponding memory location in the redundant memory sector is selected in substitution of the initially selected location; however, before being able to, e.g., read the redundant memory location, it is necessary to wait for the deselection of the initially selected location. This causes a lengthening of the access time.
Additionally, there is the risk that, during the transients caused by random accesses to the memory, one or more word lines of a defective memory sector (possibly, defective word lines that are short-circuited to ground) are accidentally selected.
In order to avoid that a defective memory sector is accidentally selected during the memory location selection transient, the memory access time has to take into account the time necessary to compare the current address code to the stored defective sector address codes. This comparison causes a non-negligible delay, particularly in the selection of the memory sectors located far from the address decoding circuitry; this is for example evident when leaving a redundant memory sector.